Current Issue : April - June Volume : 2013 Issue Number : 2 Articles : 5 Articles
Cognitive radio system (CRS) is a radio system which is aware of its operational and geographical environment, established\r\npolicies, and its internal state. It is able to dynamically and autonomously adapt its operational parameters and protocols and to\r\nlearn fromits previous experience. Based on software-defined radio (SDR), CRS provides additional flexibility and offers improved\r\nefficiency to overall spectrum use. CRS is a disruptive technology targeting very high spectral efficiency. This paper presents an\r\noverview and challenges of CRS with focus on radio frequency (RF) section.We summarize the status of the related regulation and\r\nstandardization activities which are very important for the success of any emerging technology. We point out some key research\r\nchallenges, especially implementation challenges of cognitive radio (CR). A particular focus is on RF front-end, transceiver, and\r\nanalog-to-digital and digital-to-analog interfaces which are still a key bottleneck in CRS development....
Multigigabit LDPC decoders are demanded by standards like IEEE 802.15.3c and IEEE 802.11ad. To achieve the high throughput\r\nwhile supporting the needed flexibility, sophisticated architectures are mandatory. This paper comprehensively presents the design\r\nspace for flexible multigigabit LDPC applications for the first time. The influence of various design parameters on the hardware\r\nis investigated in depth. Two new decoder architectures in a 65 nm CMOS technology are presented to further explore the design\r\nspace. In the past, the memory domination was the bottleneck for throughputs of up to 1 Gbit/s. Our systematic investigation of\r\ncolumn- versus row-based partially parallel decoders shows that this is no more a bottleneck for multigigabit architectures. The\r\nevolutionary progress in flexible multigigabit LDPC decoder design is highlighted in an extensive comparison of state-of-the-art\r\ndecoders....
This paper shows a digital noise generator designed in FPGA, based on a variant of the one-dimensional (1D) chaotic tent map\r\n(T-1D). The T-1D map is a piecewise linear 1D chaotic map that defines the statistical behavior of the generated sequences using\r\nits control parameter. In this way, the proposed noise generator is a highly competitive alternative in cryptographic systems when\r\nthe statistical behavior of the sequences is closer to the uniform statistical distribution. The proposed system uses the inverted\r\ntent chaotic map (IT-1D), which has the same statistical behavior as the T-1D map. The fundamental algorithm used in this\r\nsystem was developed based on a 64-bit double precision format according to the numerical representation of floating point\r\nnumbers defined in the IEEE-754 standard. The proposed system is analized using mechanical statistic tools and some statistical\r\ntests defined in the NIST 800-22SP (USA) standard. The main contribution of this work is the possibility of generating binary\r\nsequence of pseudorandom appearance by a procedure implemented in an FPGA device that translates real numbers to natural\r\nnumbers preserving the statistical properties of sequences of real numbers that can be generated with the tent chaotic map in its\r\noriginal definition domain....
Flexible channel decoding is getting significance with the increase in number of wireless standards and modes within a standard.\r\nA flexible channel decoder is a solution providing interstandard and intrastandard support without change in hardware. However,\r\nthe design of efficient implementation of flexible low-density parity-check (LDPC) code decoders satisfying area, speed, and power\r\nconstraints is a challenging task and still requires considerable research effort. This paper provides an overview of state-of-the-art\r\nin the design of flexible LDPC decoders. The published solutions are evaluated at two levels of architectural design: the processing\r\nelement (PE) and the interconnection structure. A qualitative and quantitative analysis of different design choices is carried out,\r\nand comparison is provided in terms of achieved flexibility, throughput, decoding efficiency, and area (power) consumption....
This work presents a flexible VLSI architecture to compute the N-point DCT. Since HEVC supports different block sizes for the\r\ncomputation of the DCT, that is, 4 Ã?â?? 4 up to 32 Ã?â?? 32, the design of a flexible architecture to support them helps reducing the area\r\noverhead of hardware implementations. The hardware proposed in this work is partially folded to save area and to get speed for\r\nlarge video sequences sizes. The proposed architecture relies on the decomposition of the DCT matrices into sparse submatrices\r\nin order to reduce the multiplications. Finally, multiplications are completely eliminated using the lifting scheme. The proposed\r\narchitecture sustains real-time processing of 1080P HD video codec running at 150 MHz....
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